Title :
Design guidelines for leakage control transistor
Author :
Farbiz, F. ; Emadi, M. ; Foruzandeh, B.
Author_Institution :
Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
Abstract :
This paper investigates the effects of transistor sizing of the sleep transistor on the power consumption and speed. A method is proposed to handle the power-delay trade off and a new transistor arrangement is proposed. Simulations show how much is the appropriate size of sleep transistor with respect to the gate size. This paper deals with the effective combination of stack transistor insertion method and the input vector control technique. Sizing considerations for both the proposed and conventional methods are examined.
Keywords :
MOSFET; leakage currents; logic gates; logic simulation; input vector control technique; leakage control transistor design; logic gates; logic simulation; power consumption; power delay trade off; sleep transistor; stack transistor insertion method; transistor sizing effects; Batteries; Circuits; Energy consumption; Guidelines; MOS devices; Power engineering and energy; Power engineering computing; Threshold voltage; Transistors; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on
Conference_Location :
Montreal, Quebec, Canada
Print_ISBN :
0-7803-8322-2
DOI :
10.1109/NEWCAS.2004.1359063
