Design guidelines for leakage control transistor

This paper investigates the effects of transistor sizing of the sleep transistor on the power consumption and speed. A method is proposed to handle the power-delay trade off and a new transistor arrangement is proposed. Simulations show how much is the appropriate size of sleep transistor with respect to the gate size. This paper deals with the effective combination of stack transistor insertion method and the input vector control technique. Sizing considerations for both the proposed and conventional methods are examined.