On low power shift register hardware realizations for convolutional encoders and decoders

Novel methods to implement low power hardware architectures comprising several different kinds of shift registers in FPGAs are presented. These methods lead to shift register structures with reduced power dissipation. The proposed structures are particularly effective to reduce the power dissipation for medium and large shift register lengths. A systematic method to select the best shift register structure within a given configuration is also proposed. The proposed structures and selection method are generic, but they are well suited for implementing powerful encoders and decoders associated with forward error correction techniques, such as convolutional coding and iterative threshold decoding.