Speed and area trade-offs for FPGA-based implementation of RSA architectures

In this paper, new structures that implement RSA cryptographic algorithm are presented. These structures are built upon a modified Montgomery modular multiplier, where the operations of multiplication and modular reduction are carried out in parallel rather than interleaved as in the traditional Montgomery multiplier. The digit approach has been adopted in this paper. This methodology is based on varying the digit size and the level of pipelining of the structures. This parameterised approach presents the designer with an efficient way of choosing the architecture which suits better the user requirements in terms of speed and area usage, an issue of critical importance to the resources-limited FPGA chips. Furthermore, the global broadcast data lines are avoided by interleaving multiple encryption operations into the same structure, thus making the implementation systolic. The results of implementation in FPGA have shown that the proposed RSA structures outperformed those structures built around the traditional Montgomery multiplier in terms of speed and area usage.