Title :
Damascene stud local interconnect in CMOS technology
Author :
White, F. ; Hill, W. ; Eslinger, S. ; Payne, E. ; Cote, W. ; Chen, B. ; Johnson, K.
Author_Institution :
IBM Corp., Essex Junction, VT, USA
Abstract :
Localized interconnects are key to reducing the cell size of SRAMs as well as providing improved densities for logic circuits. A planar local interconnect featuring a damascene W stud metallurgy is described. Features of the damascene process include borderless contacts to both wordlines and diffusion, contact to the local interconnect, reduced topography, and low resistivity. The borderless contact feature is accomplished by incorporation of an etch stop. Chemical-mechanical polishing is used to planarize the dielectric passivation and W fills.<>
Keywords :
CMOS integrated circuits; SRAM chips; integrated circuit technology; integrated logic circuits; metallisation; passivation; polishing; tungsten; CMOS technology; SRAMs; W; borderless contacts; cell size; chemical-mechanical polishing; circuit densities; damascene W stud local interconnect; dielectric passivation; etch stop; logic circuits; resistivity; topography; wordlines; CMOS integrated circuits; Integrated circuit fabrication; Metallization; Passivation; SRAM chips; Tungsten;
Conference_Titel :
Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1992.307365
