DocumentCode
1952551
Title
Design trade-offs for a 10 bit, 80 MHz current steering digital-to-analog converter
Author
Baschirotto, A. ; Ghittori, N. ; Malcovati, P. ; Vigna, A.
Author_Institution
Dept. of Innovation Eng., Lecce Univ., Italy
fYear
2004
fDate
20-23 June 2004
Firstpage
249
Lastpage
252
Abstract
This paper presents the trade-offs in dimensioning a 10 bit, 80 MHz current steering DAC for wireless-LAN transmitters. All the performance parameters are considered, trying to optimize static performance, dynamic performance and area occupation. Behavioral and transistor level simulations are then used to validate the proposed mathematical analysis.
Keywords
CMOS integrated circuits; circuit simulation; digital-analogue conversion; mathematical analysis; radio transmitters; wireless LAN; 80 MHz; CMOS integrated circuits; circuit optimisation; current steering DAC; current steering digital-analog converter; dynamic performance; mathematical analysis; static performance; transistor level simulations; wireless LAN transmitters; Analytical models; Cutoff frequency; Digital-analog conversion; Filters; Frequency conversion; Linearity; Mathematical analysis; Radio frequency; Radio transmitters; Wireless LAN;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on
Print_ISBN
0-7803-8322-2
Type
conf
DOI
10.1109/NEWCAS.2004.1359078
Filename
1359078
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