• DocumentCode
    1952556
  • Title

    Novel process techniques for fabricating high density trench MOSFETs with self-aligned N+/P+ source formed on the trench side wall

  • Author

    Park, Il-Yong ; Kim, Sang-Gi ; Koo, Jin-Gun ; Kim, Jongdae

  • Author_Institution
    Basic Res. Lab., Electron. & Telecommun. Res. Inst., Daejeon, South Korea
  • fYear
    2003
  • fDate
    14-17 April 2003
  • Firstpage
    169
  • Lastpage
    172
  • Abstract
    Novel process techniques for fabricating highly dense trench MOSFETs are proposed and verified by experimental and numerical results. P+ region for p-base contact and N+ source are formed on the trench side wall by using self-aligned process techniques including triple trench etching. Two-dimensional process and device simulation is performed by using SILVACO with the cell pitch of 1.0 μm for the proposed trench MOSFET. The simulated breakdown voltage and on-resistance are 45 V and 12.9 mΩ-mm2, respectively.
  • Keywords
    etching; p-n junctions; power MOSFET; semiconductor device breakdown; semiconductor device models; 1.0 micron; 45 V; cell pitch; device simulation; high density trench MOSFET; p-base contact; self-aligned N+/P+ source; self-aligned process technique; simulated breakdown voltage; trench side wall; triple trench etching; two-dimensional process; Application software; Boron; Computational modeling; DC-DC power converters; Etching; Laboratories; MOSFETs; Power electronics; Silicon; Substrates;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Power Semiconductor Devices and ICs, 2003. Proceedings. ISPSD '03. 2003 IEEE 15th International Symposium on
  • Print_ISBN
    0-7803-7876-8
  • Type

    conf

  • DOI
    10.1109/ISPSD.2003.1225256
  • Filename
    1225256
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1952556