Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variations

We show NBTI delay degradation considering variations in a 65 nm process. We evaluate these two models. The homogeneous degradation model (HDM) assumes that NBTI degradation is constant at any variation and the inhomogeneous degradation model (IDM) assume that it is larger at the fast condition. In the usual logic gates on ASICs, delay degradation becomes much smaller on IDM. Circuit design guardbands can be reduced to 1/3 from the conventional pessimistic evaluations. As for FPGAs, we evaluate routing paths including level restorers and tristate inverters. The delay time after NBTI degradation is almost constant because of the pull-up PMOS in the level restorer.