Design of a constant geometry fast Hartley transformer

A semisystolic architecture is presented for the parallel calculation of the decimation in time and radix-2 fast Hartley transform (FHT) of a real sequence with N=2ⁿ data items. The architecture is based on a constant geometry algorithm for computing the FHT which facilitates its mapping in VLSI technology and minimizes the communications among processors. The circuit proposed is characterized by its modular design and its interconnective regularity. It permits the computation of arbitrarily sized FHTs as a consequence of the partition of the data and the recirculation of partial results over the processing units in the successive stages of the transform. Each calculation stage requires N/4Q cycles where Q is the number of processors (Q=2^q). The total calculation time is ( Nlog₂N)/4Q cycles