Abstract :
A new family of semiconductor packages, referred to as VSPATM , is described which combines unique 3D design features and materials technology selection to produce superior electrical, thermal and mechanical performance for both single and multiple chip modules. These packages are readily scalable to accommodate a wide variety of footprint, shape, I/O (up to 1000) and bandwidth requirements at very low cost ($0.01). The unique design and fabrication method eliminates the die leadframe, allowing a smaller footprint, relaxed lead pitch, and robust leads with improved coplanarity. The I/O pins are a constant regardless of the package frame size, which provides a low inductance path from die to PCB. The peripheral lead structure allows for visual inspection and ease of rework. The die attaches in a flip chip manner to a metallic plate, an integral part of the package, providing a direct thermal path to ambient or cooling devices. The 3D stacking of the leads results in significant size reduction, low inductance paths, with the pin design providing reduced package parasitics and allowing resonance free operation up to 3.5 GHz. Techniques for 3D chip stacking are described as well as environmental test results, standard activity, and novel heatsink designs. A liquid crystal polymer frame provides excellent stability with a 335°C melt point, and allows for tolerances of less than 1 mil to be held for pin alignment and coplanarity in high volume manufacturing environments
Keywords :
environmental testing; flip-chip devices; heat sinks; integrated circuit design; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; liquid crystal polymers; multichip modules; thermal management (packaging); 3.5 GHz; 335 C; 3D chip stacking; 3D design features; 3D lead stacking; I/O pins; VSPA 3D semiconductor packages; cooling devices; coplanarity tolerance; die attach; die leadframe; die-to-PCB path inductance; direct thermal path; electrical performance; environmental test; flip chip; heatsink design; lead coplanarity; lead pitch; liquid crystal polymer frame; materials technology selection; mechanical performance; melt point; metallic plate; multiple chip modules; package I/O; package bandwidth; package fabrication; package footprint; package frame size; package parasitics; package shape; package size reduction; peripheral lead structure; pin alignment tolerance; pin design; resonance free operation; rework; robust leads; semiconductor packages; single chip modules; stability; thermal performance; visual inspection; volume manufacturing; Bandwidth; Costs; Design methodology; Fabrication; Inductance; Materials science and technology; Robustness; Semiconductor device packaging; Shape; Stacking;
