DocumentCode
1952718
Title
Quasi-SOI MOSFETs using selective epitaxy and polishing
Author
Nguyen, C.T. ; Kuehne, S.C. ; Renteln ; Wong, S.S.
Author_Institution
Center for Integrated Syst., Stanford Univ., CA, USA
fYear
1992
fDate
13-16 Dec. 1992
Firstpage
341
Lastpage
344
Abstract
A Quasi-SOI MOSFET structure has been fabricated in which the drain-side channel is placed over oxide while the source-side channel is left connected to the substrate. This device has many of the advantages of SOI MOSFET without some of its problems. In particular, the drain breakdown voltage is found to improve over both the bulk and the complete-SOI counterparts. It is confirmed that the maximum lateral electric field is lower in the SOI channel than in same-size bulk device. The selective epitaxy and polishing technology combination used here makes it possible to fabricate all device types ranging from bulk to quasi-SOI to complete SOI on the same substrate, thus facilitating meaningful comparative studies.<>
Keywords
epitaxial growth; insulated gate field effect transistors; polishing; semiconductor technology; semiconductor-insulator boundaries; drain breakdown voltage; drain-side channel; lateral electric field; polishing; quasi-SOI MOSFET; selective epitaxy; source-side channel; Epitaxial growth; Insulated gate FETs; Semiconductor device fabrication; Semiconductor-insulator interfaces;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International
Conference_Location
San Francisco, CA, USA
ISSN
0163-1918
Print_ISBN
0-7803-0817-4
Type
conf
DOI
10.1109/IEDM.1992.307374
Filename
307374
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