170V Super Junction - LDMOST in a 0.5 μm commercial CMOS/SOS technology

Author

Nassif-Khalil, S.G. ; Salama, C. Andre T

Author_Institution

Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada

fYear

2003

fDate

14-17 April 2003

Firstpage

228

Lastpage

231

Abstract

This paper reports on an experimental 170V Super Junction - LDMOST (SJ-LDMOST) implemented in a 0.5 μm CMOS/SOS technology developed primarily for low voltage RF and mixed signal applications. An experimental SJ-LDMOST with a drift region length of 10 μm and a drift region pillar doping concentration of ∼2x10¹⁷cm^-3 exhibits a breakdown voltage of 170 V. The high average lateral electric field of 17V/μm implies that (near) charge compensation, between the alternating polarity pillars, has been achieved. 3D device simulations predict that the silicon limit in conventional LDMOSTs can be broken when the aspect ratio of pillar height to width exceeds 1.2 μm/0.3 μm.

Keywords

CMOS integrated circuits; low-power electronics; mixed analogue-digital integrated circuits; power integrated circuits; semiconductor device breakdown; semiconductor device models; silicon-on-insulator; 0.5 micron; 170 V; 3D device simulation; CMOS/SOS technology; alternating polarity pillar; aspect ratio; breakdown voltage; charge compensation; drift region length; drift region pillar doping concentration; lateral electric field; low voltage RF; mixed signal application; super junction LDMOST; Breakdown voltage; CMOS technology; Crystallization; Design optimization; Doping; MOS devices; Ohmic contacts; Silicon; Stacking; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 2003. Proceedings. ISPSD '03. 2003 IEEE 15th International Symposium on

Print_ISBN

0-7803-7876-8

Type

conf

DOI

10.1109/ISPSD.2003.1225270

Filename

1225270