Sub-20 ps silicon bipolar technology using selective epitaxial growth

Author

Meister, T.F. ; Stengl, R. ; Meul, H.W. ; Weyl, R. ; Packan, P. ; Felder, A. ; Klose, H. ; Schreiter, R. ; Popp, Jurgen ; Rein, H.M. ; Treitinger, L.

Author_Institution

Corp. Res. & Dev., Siemens AG, Munich, Germany

fYear

1992

fDate

13-16 Dec. 1992

Firstpage

401

Lastpage

404

Abstract

A sub-20 ps silicon bipolar technology has been developed using selective epitaxial growth (SEG) for the active base and collector regions. This transistor concept allows the simultaneous reduction of base width and base/collector capacitance while maintaining low extrinsic base resistance. At a current of 0.8 mA a record CML gate delay time of 18 ps is achieved with devices showing a cut-off frequency of 44 GHz. The high-speed capability of this technology has also been shown by a static 2:1 frequency divider operating up to 25 GHz.<>

Keywords

bipolar integrated circuits; delays; elemental semiconductors; emitter-coupled logic; epitaxial growth; integrated circuit technology; integrated logic circuits; semiconductor growth; silicon; 0.8 mA; 18 to 20 ps; 25 GHz; 44 GHz; CML gate delay time; Si; base width; base/collector capacitance; bipolar technology; high-speed capability; selective epitaxial growth; static frequency divider; Bipolar integrated circuits; Delay effects; Emitter coupled logic; Epitaxial growth; Integrated circuit fabrication; Semiconductor growth; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1992.307387

Filename

307387