Characterization of stress induced defects in deep sub-micron MOSFETS

This paper investigates parasitics associated with MOS devices in sub-micron regime and the main mechanisms involved in p-n junctions and oxide breakdowns, as well as punch-through events. The results of measured destructive and non-destructive breakdown voltages for MOS devices of different types and channel sizes are presented. These measurements are obtained from limited number of samples using different test setups under a systematic test protocol at the ambient temperature. Our characterization were conducted on the 0.18 μm N-well CMOS process from TSMC. It is shown that carrier distribution in channel has a significant impact on device characteristics. It was also found that gate oxide breakdown at drain/source edges are independent on device geometry, while breakdown between gate and channel is strongly dependent on it. Finally, the results allow the MOS device to perform at voltage levels up to twice the process power supply.