• DocumentCode
    1953010
  • Title

    Design of reconfigurable general finite field multiplier in GF (2m)

  • Author

    Li, Hua

  • Author_Institution
    Dept. of Math. & Comput. Sci., Lethbridge Univ., Alta., Canada
  • fYear
    2004
  • fDate
    20-23 June 2004
  • Firstpage
    337
  • Lastpage
    339
  • Abstract
    In this paper, a general finite field multiplier is presented which can he used in any basis by simple configuration. It significantly increases the flexibility such that the same multiplier can be used in different applications and reduces the user´s cost. The proposed multiplier has a regular structure and is very suitable for high speed VLSI implementation.
  • Keywords
    VLSI; cost reduction; high-speed integrated circuits; matrix algebra; reconfigurable architectures; cost reduction; high speed VLSI implementation; matrix algebra; reconfigurable general finite field multiplier; Costs; Cryptography; Galois fields; Hardware; Mathematics; Matrix converters; Polynomials; Switches; Switching converters; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on
  • Print_ISBN
    0-7803-8322-2
  • Type

    conf

  • DOI
    10.1109/NEWCAS.2004.1359100
  • Filename
    1359100
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1953010