Title :
Design of reconfigurable general finite field multiplier in GF (2m)
Author_Institution :
Dept. of Math. & Comput. Sci., Lethbridge Univ., Alta., Canada
Abstract :
In this paper, a general finite field multiplier is presented which can he used in any basis by simple configuration. It significantly increases the flexibility such that the same multiplier can be used in different applications and reduces the user´s cost. The proposed multiplier has a regular structure and is very suitable for high speed VLSI implementation.
Keywords :
VLSI; cost reduction; high-speed integrated circuits; matrix algebra; reconfigurable architectures; cost reduction; high speed VLSI implementation; matrix algebra; reconfigurable general finite field multiplier; Costs; Cryptography; Galois fields; Hardware; Mathematics; Matrix converters; Polynomials; Switches; Switching converters; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on
Print_ISBN :
0-7803-8322-2
DOI :
10.1109/NEWCAS.2004.1359100
