Cost-effective approach in LDMOS with partial 0.35μm design into conventional 0.6μm process

We propose a practical solution, which can provide the same high performance LDMOS as that of the more advanced CMOS design rule with retaining still the low cost of the old technology. More specifically, we have introduced a limited number of 0.35μm equivalent mask alignment steps into 0.6μm based BCD processes. We have successfully developed 0.6μm design based 40V and 50V LDMOS, whose on-resistances are superior to those of 0.35μm based LDMOS. The on-resistance of the developed 40V and 50V LDMOS are 54.3 and 69.7 mΩ mm², respectively. These values are superior to the reported values of the 0.35μm design LDMOS.