DocumentCode :
1953062
Title :
CarlOthello : An FPGA-Based Monte Carlo Othello player
Author :
Smerdis, Miltiadis ; Malakonakis, Pavlos ; Dollas, Apostolos
Author_Institution :
Dept. of Electron. & Comput. Eng., Tech. Univ. of Crete, Chania, Greece
fYear :
2010
fDate :
8-10 Dec. 2010
Firstpage :
515
Lastpage :
518
Abstract :
In the FPT 2010 International Conference an Othello competition has been announced, based on the popular game and with requirements for implementation of full designs on standardized FPGA platforms. This paper presents in detail the CarlOthello architecture and design, which is heavily pipelined in order to increase the expansion rate of the overall system, reaching a peak of 4×108 expansions per second. The Monte Carlo-based Othello player was fully designed, implemented in hardware, and tested. This design wins every game against the FPT 2010 reference software.
Keywords :
Monte Carlo methods; computer games; field programmable gate arrays; CarlOthello; CarlOthello architecture; FPGA-based Monte Carlo Othello player; Clocks; Computer architecture; Field programmable gate arrays; Games; Hardware; Monte Carlo methods; Software;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Technology (FPT), 2010 International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-8980-0
Type :
conf
DOI :
10.1109/FPT.2010.5681471
Filename :
5681471
Link To Document :
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