Built-in self-test design of motion estimation computing array

Author

Donglin, Li. ; Hu, Mingzeng ; Mohamed, Otmane Ait

Author_Institution

Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada

fYear

2004

fDate

20-23 June 2004

Firstpage

349

Lastpage

352

Abstract

This paper presents an implementation of built-in self-test (BIST) design of motion estimation (ME) computing array, which is the main part of MPEG-2 video encoder. The goal of the design is to offer high reliability for the coding system. Our design is carried out on gate level in both VHDL and Verilog HDL and then synthesized into FPGA. Design verification is also performed using logic simulation and fault simulation.

Keywords

built-in self test; fault simulation; field programmable gate arrays; hardware description languages; logic simulation; motion estimation; reliability; shift registers; video coding; BIST; FPGA; MPEG-2 video encoder; VHDL; Verilog HDL; built-in self test; coding system; fault simulation; logic simulation; motion estimation computing array; reliability; shift registers; Built-in self-test; Circuit testing; Design for testability; Hardware design languages; Logic testing; Motion estimation; Pattern analysis; System testing; Test pattern generators; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on

Print_ISBN

0-7803-8322-2

Type

conf

DOI

10.1109/NEWCAS.2004.1359104

Filename

1359104

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1953071