Title :
Logic minimization for factored forms
Author :
Malik, Abdul A. ; Brayton, Robert K. ; Sangiovanni-Vincentelli, Alberto L.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
The minimization of Boolean functions is usually aimed at obtaining a minimum sum-of-products representation, measured in terms of the number of product terms produced. In multilevel logic, however, a better objective function is a minimized factored form. Traditionally, logic functions have been factored by using algebraic techniques on a minimized sum-of-products. Algebraic factorization techniques explore only part of the solution space. A technique for factoring based on Boolean operations is presented. This technique often leads to a better factored form for a logic function. The algorithm uses the Boolean operations which are the basis of the two-level minimizer ESPRESSO. The technique has been implemented in the multilevel logic minimization program MIS. Some results of Boolean factorization of individual nodes in multilevel networks are presented and then compared with other factoring methods in MIS
Keywords :
Boolean functions; logic CAD; minimisation; Boolean factorization; Boolean functions; Boolean operations; ESPRESSO; MIS; factored forms; factoring; logic functions; minimum sum-of-products representation; multilevel logic minimization program; multilevel networks; nodes; objective function; product terms; two-level minimizer; Boolean functions; Filters; Ice; Logic functions; Minimization methods; Rails;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63395