High performance SCRs for on-chip ESD protection in high voltage BCD processes

Author

Vashchenko, V.A. ; Concannon, A. ; Beek, M. Ter ; Hopper, P.

Author_Institution

Nat. Semicond. Corp., Santa Clara, CA, USA

fYear

2003

fDate

14-17 April 2003

Firstpage

261

Lastpage

264

Abstract

ESD protection structures based on triggering devices for on-chip ESD protection in a 100V BCD process have been designed and analyzed using physical process and device simulation (TCAD), followed by pulse measurements of test-structures. Based on the resultant data a self-protecting high-voltage bipolar SCR structure with a ten-fold increase in the protection level compared to the reference BJT was developed. The effect of blocking the N-buried layer (NBL) was found to be critical for stable ESD operation.

Keywords

BiCMOS integrated circuits; electrostatic discharge; integrated circuit reliability; thyristors; N-buried layer blocking; device simulation; high performance SCR; high voltage BCD processes; high-voltage bipolar SCR; on-chip ESD protection; physical process; pulse measurements; self-protecting bipolar SCR; test structures; Analytical models; BiCMOS integrated circuits; Breakdown voltage; Conductivity; Electrostatic discharge; Equations; Isothermal processes; Process design; Protection; Thyristors;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 2003. Proceedings. ISPSD '03. 2003 IEEE 15th International Symposium on

Print_ISBN

0-7803-7876-8

Type

conf

DOI

10.1109/ISPSD.2003.1225278

Filename

1225278