DocumentCode
1953085
Title
Combining advanced process technology and design for systems level integration
Author
Hunter, Ana ; Lau, CK ; Martin, John
Author_Institution
Chartered Semicond. Manuf. Ltd., Singapore
fYear
2000
fDate
2000
Firstpage
245
Lastpage
250
Abstract
Recent advances in process and integration are enabling systems level integration for numerous applications. The quality of the systems depends directly on the quality of the processes and effectiveness of the process integration, and on the quality of the designs and libraries employed, as well as on the completeness and accuracy of the models used to link the process and designs. Unit process and process module quality is ensured through the use of designed experimentation, margin analysis, and statistical capability measurement. The link between the processes and the libraries and designs is formed through such models as SPICE and interconnect, with quality implications associated with the extraction and implementation. GDSII algorithms to incorporate process specific post layout features such as OPC and fill patterns for CMP planarization are integrated into the CAD flow prior to final verification, reticle manufacturing and silicon prototyping. Foundry specific challenges in providing process and library elements include multiple design flows, tool providers and library suppliers. Examples of approaches to quality designs, processes and systems are presented using advanced cores and systems level integration
Keywords
SPICE; circuit CAD; integrated circuit design; integrated circuit modelling; semiconductor process modelling; statistical analysis; CAD flow; CMP planarization; GDSII algorithms; SPICE modelling; advanced process design; advanced process technology; library elements; margin analysis; process characterisation; process module quality; process specific post layout features; statistical capability measurement; systems level integration; unit process quality; Computer aided manufacturing; Design automation; Libraries; Manufacturing processes; Planarization; Process design; Prototypes; SPICE; Semiconductor device modeling; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Quality Electronic Design, 2000. ISQED 2000. Proceedings. IEEE 2000 First International Symposium on
Conference_Location
San Jose, CA
Print_ISBN
0-7695-0525-2
Type
conf
DOI
10.1109/ISQED.2000.838879
Filename
838879
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