Title :
A high performance BiCMOS process featuring 40 GHz/21 ps
Author :
Kerber, M. ; Bertagnolli, E. ; Mahnkopf, R. ; Popp, J. ; Felder, A. ; Rein, H.M. ; Weisgerber, A. ; Klose
Author_Institution :
Corp. Res. & Dev., Siemens AG, Munich, Germany
Abstract :
A high performance BiCMOS process is presented which features 40 GHz cutoff frequency, 21 ps gate delay and 20 GHz divider circuits for the bipolar part together with 0.6 mu m CMOS. Deep trench isolation is used for low collector to substrate capacitances and high packing density. Concepts to decouple the bipolar from the CMOS building blocks for an uncompromised optimization of both device types are proposed and discussed.<>
Keywords :
BiCMOS integrated circuits; digital integrated circuits; integrated circuit technology; 0.6 micron; 20 GHz; 21 ps; 40 GHz; BiCMOS process; CMOS building blocks; cutoff frequency; deep trench isolation; divider circuits; gate delay; high packing density; high performance process; BiCMOS integrated circuits; Digital integrated circuits; Integrated circuit fabrication;
Conference_Titel :
Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1992.307398
