Title :
On testability of multiple precharged domino logic
Author :
Haniotakis, Th ; Tsiatouhas, Y. ; Nikolos, D. ; Efstathiou, C.
Author_Institution :
ISD SA, Halandri, Greece
Abstract :
Domino circuits are increasingly popular because they offer a significant performance boost over static ones. An inherent problem with domino CMOS gates is that under specific input conditions the charge redistribution between parasitic capacitances at internal nodes of the circuit can destroy the noise margin and cause glitches at the output of a domino gate. Among the dominant solutions proposed, in the open literature, to overcome this problem is the technique of internal nodes multiple precharging. However the added precharge transistors are not testable for stuck-open and stuck-on faults. Undetectable stuck-open faults on these transistors cause reduction of the noise margins of the gate. Then the operation of the circuit in the field is sensitive to environmental factors, such as noise. In this paper we propose a new internal nodes multiple precharging scheme that leads to testable designs for stuck-open and stuck-on faults
Keywords :
CMOS logic circuits; capacitance; fault diagnosis; integrated circuit noise; integrated circuit testing; logic gates; logic testing; charge redistribution; domino CMOS gates; environmental factors; glitches; multiple precharged domino logic; noise margin; noise margins; parasitic capacitances; specific input conditions; stuck-on faults; stuck-open faults; testability; testable designs; CMOS logic circuits; Circuit faults; Circuit noise; Circuit testing; Informatics; Inverters; Logic testing; MOS devices; Semiconductor device modeling; Working environment noise;
Conference_Titel :
Quality Electronic Design, 2000. ISQED 2000. Proceedings. IEEE 2000 First International Symposium on
Conference_Location :
San Jose, CA
Print_ISBN :
0-7695-0525-2
DOI :
10.1109/ISQED.2000.838886
