DocumentCode
1953289
Title
PRMC: a multicontext FPGA with partially reconfigurable logic planes
Author
Smith, Jack R. ; Xia, Tian
Author_Institution
IBM Corp., Essex Junction, VT, USA
fYear
2004
fDate
20-23 June 2004
Firstpage
393
Lastpage
396
Abstract
Multicontext field programmable gate arrays (FPGAs) are excellent devices to use in reconfigurable computing systems for boosting performance. In addition, multicontext devices can save space compared to the conventional FPGAs because they store more programming data per area. However, multicontext FPGAs suffer the same long configuration delays as conventional FPGAs, and this limits performance in some situations. To solve that problem, we introduce a new FPGA called PRMC. The PRMC FPGA is an enhanced multicontext design that has partially reconfigurable contexts and additional features to reduce the configuration overhead. As a result, PRMC configures faster than present multicontext FPGAs, while enjoying the same area benefit. This paper describes the architecture of our PRMC FPGA.
Keywords
field programmable gate arrays; logic design; reconfigurable architectures; configuration overhead reduction; delays; logic design; multicontext devices; multicontext field programmable gate arrays; partially reconfigurable logic planes; partially reconfigurable multicontext FPGA; reconfigurable computing systems; Boosting; Costs; Delay; Fabrics; Field programmable gate arrays; Lifting equipment; Logic programming; Programmable logic arrays; Random access memory; Reconfigurable logic;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. NEWCAS 2004. The 2nd Annual IEEE Northeast Workshop on
Print_ISBN
0-7803-8322-2
Type
conf
DOI
10.1109/NEWCAS.2004.1359118
Filename
1359118
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