An Approach to Instruction Set Compiled Simulator Development Based on a Target Processor C Compiler Back-End Design

Many instruction set simulation approaches place the retargetability and/or cycle-accuracy as the key features for easier architectural exploration and performance estimation early in the hardware development phase. This paper describes an approach in which importance of speed and controllability is placed above the cycle-accuracy and retargetability, thus providing a better platform for software development. The main idea behind this work is to try to associate the compiled simulator effort with the development of the C language compiler for the target embedded processor, using the knowledge from that field of work and reusing some common software elements. Through the prototype design of a compiled simulator for the Cirrus Logic Coyote DSP architecture, many implementation aspects are presented proving that this approach has a great potential.