A physical model for MOSFET output resistance

Author

Huang, J.H. ; Liu, Z.H. ; Jeng, M.C. ; Ko, P.K. ; Hu, C.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1992

fDate

13-16 Dec. 1992

Firstpage

569

Lastpage

572

Abstract

The output resistance (R/sub out/) most important device parameters for analog applications. However, it has been difficult to model R/sub out/ correctly. In this paper, we present a physical and accurate output resistance model that can be applied to both long-channel and submicrometer MOSFETs. Major short channel effects and hot-carrier effect, such as channel-length modulation (CLM), drain-induced-barrier-lowering (DIBL) and substrate current induced output resistance reduction, are all included in this model, and it is scalable with respect to different channel length L, gate oxide thickness T/sub ox/ and power supply V/sub dd/. This model can be incorporated into existing MOSFET´s model without introducing discontinuity.<>

Keywords

electric resistance; hot carriers; insulated gate field effect transistors; semiconductor device models; MOSFET output resistance; channel length; channel-length modulation; drain-induced-barrier-lowering; gate oxide thickness; hot-carrier effect; long-channel device; physical model; power supply; short channel effects; submicron device; substrate current induced output resistance reduction; Hot carriers; Insulated gate FETs; Resistance; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1992.307426

Filename

307426