DocumentCode
1953956
Title
Design of t-UED/AUED codes from Berger´s AUED code
Author
Biswas, Gosta Pada ; Sengupta, Indranil
Author_Institution
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
fYear
1997
fDate
4-7 Jan 1997
Firstpage
364
Lastpage
369
Abstract
Berger code has been extended in this paper to construct optimal t-UED/AUED codes for t=1, 2 and 3. The resulting codes are similar to some existing codes. A generalization of Bose´s method (1991) has been shown on extending Berger code into AUED code (with r check bits for 2 r information bits). Further extension of Berger code results in an efficient (t+1)-UED code with t check bits, where a combined approach of the two extensions of generating t-UED and AUED code from Berger code has been applied. Finally, a very simple and regular hardware implementation of the encoder/decoder has been proposed
Keywords
VLSI; combinational circuits; decoding; delays; error detection codes; integrated logic circuits; logic design; AUED code; Berger code; design complexity; encoder/decoder; hardware implementation; t-UED code; Circuits; Computer errors; Computer science; Decoding; Hardware; Modular construction; Protection; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location
Hyderabad
ISSN
1063-9667
Print_ISBN
0-8186-7755-4
Type
conf
DOI
10.1109/ICVD.1997.568154
Filename
568154
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