Device mismatch analysis and effect compensation in fundamental analog cells

The operation of highly complex analog ICs is strongly affected by the non-idealities inherently induced in modern sub-micron production technologies. Extensive testing has proven that process mismatch of small geometry transistors has the strongest effect on production yield. The aim of this article is to propose a methodology to analyze and compensate the effects of mismatch on the functionality of basic analog building blocks, which will be reflected in the operation and performance of more complex analog ICs. The novelty of this paper is the bi-univocal treatment of mismatch cause and effect, along with the appropriate optimization strategy. The analysis methodology is developed around Monte Carlo simulation to estimate statistical data regarding post-production IC performance, and consequently production yield. Further on, means of compensation towards error enhancement are investigated and proven on basic analog building blocks, as well as on a fully differential folded-cascode operational transconductance amplifier.