Title :
Generation, verification, and execution of boundary scan with built-in self-test hardware for VLSI
Author :
Ryan, Christopher A. ; Martin, Harold L.
Author_Institution :
North Carolina A&T State Univ., Greensboro, NC, USA
Abstract :
Some of the problems traditionally associated with design-for-testability are the complexity of integrating the needed hardware, the verification and execution of this hardware, and the area overhead required for such an integration. A VLSI CAD tool that generates a layout for such hardware for any CMOS chip is presented. A method for verifying fault-free operation and an execution protocol procedure for the hardware are also presented
Keywords :
CMOS integrated circuits; VLSI; built-in self test; circuit layout CAD; integrated circuit testing; CAD tool; CMOS chip; VLSI; boundary scan; built-in self-test hardware; design-for-testability; execution; execution protocol; fault-free operation; layout; verification; Built-in self-test; Circuit testing; Clocks; Design automation; Design for testability; Hardware; Pins; Registers; System testing; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1989., Proceedings of the 32nd Midwest Symposium on
Conference_Location :
Champaign, IL
DOI :
10.1109/MWSCAS.1989.101790
