High carrier velocity and reliability of quarter-micron SPI (Self-aligned Pocket Implantation) MOSFETs

A novel SPI (Self-aligned Pocket Implantation) technology has been presented, which improves short channel characteristics without increasing junction capacitance. This technology features a localized pocket implantation using gate electrode and TiSi2 film as self-aligned masks. An epi substrate is used to decrease the surface impurity concentration in the well, while maintaining high latch-up immunity. Since the SPI and the gate to drain overlapped structure such as LATID (Large Angle Tilt Implanted Drain) technology allow use of the low impurity concentration in the channel region, the carrier velocity reaches to 8*10/sup 6/ cm/sec. It is found that the SPI has no significant effect on hot carrier degradation for LATID structure. This technology yields an unloaded CMOS inverter delay per stage of 30 psec and low power dissipation.<>