A custom VLSI architecture for low-delay speech coding

A custom VLSI architecture for implementing low-delay speech coding algorithms is presented. The architecture consists of a variable number of adaptive arithmetic units (AAUs) in parallel; each AAU has an adaptive datapath to perform the required filtering operations on one element (sample) of data. The number of AAUs is optimized for power consumption and chip area. A configuration with 4 AAUs provides a good tradeoff between low power and small area. It implements the lattice low-delay vector excitation coding algorithm with an estimated power consumption of less than 300 mW and area of 90 mm², which compares favorably with implementations on general-purpose DSP chips