DocumentCode
1954762
Title
DSP image process with optimized data schedule model
Author
Yao Si-Cong ; Zhang Zhi-Jiang ; Wei, Wen ; Zeng Dan
Author_Institution
Key Lab. of Specialty Fiber & Opt. Access Networks, Shanghai Univ., Shanghai, China
Volume
1
fYear
2010
fDate
9-11 July 2010
Firstpage
393
Lastpage
398
Abstract
This paper introduces a DSP optimization model based on data structure transformation and memory schedule for real-time image process. This model implements 4 critical methods: image block, image dimension reduction, DMA transfer and ping-pong cache, which makes use of DSP hardware feature and optimizes the data schedule among the external and internal memory and CPU, while processing 2D digital signal such as images and video frames. This model provides a common strategy which can be used in the most of linear image process circumstances. Based on this model, this paper optimized a grayscale image matching algorithm and improved its efficiency, in order to verify the effectiveness of this model.
Keywords
cache storage; data structures; digital signal processing chips; image matching; optimisation; real-time systems; DMA transfer; DSP image processing; DSP optimization model; data schedule model; data structure transformation; digital signal; grayscale image matching algorithm; image block; image dimension reduction; memory schedule; ping-pong cache; real-time image processing; Correlation; Image segmentation; DMA; DSP; data structure; image matching; memory schedule; ping-pong cache;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Science and Information Technology (ICCSIT), 2010 3rd IEEE International Conference on
Conference_Location
Chengdu
Print_ISBN
978-1-4244-5537-9
Type
conf
DOI
10.1109/ICCSIT.2010.5564875
Filename
5564875
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