Title :
A Split-Level Diagonal Bit-line (SLDB) stacked capacitor cell for 256 Mb DRAMs
Author :
Hamada, T. ; Tanabe, N. ; Watanabe, H. ; Takeuchi, K. ; Kasai, N. ; Hada, H. ; Shibahara, K. ; Tokashiki, K. ; Nakajima, K. ; Hirasawa, S. ; Ikawa, E. ; Saeki, T. ; Kakehashi, E. ; Ohya, S. ; Kunio, T.
Author_Institution :
Microelectron. Res. Labs., NEC Corp., Japan
Abstract :
A Split-Level Diagonal Bit-line (SLDB) stacked capacitor cell having a cylindrical storage node with hemispherical grained (HSG) silicon is proposed for 256 MbDRAMs. This memory cell provides large alignment tolerance between contact hole and wiring, large word-line noise immunity and large storage capacitance in a small cell area of 0.54 mu m/sup 2/ with 0.25 mu m design rule.<>
Keywords :
DRAM chips; VLSI; cellular arrays; 0.25 micron; 256 Mbit; DRAMs; alignment tolerance; contact hole; cylindrical storage node; design rule; hemispherical grained silicon; small cell area; split-level diagonal bit-line; stacked capacitor cell; storage capacitance; wiring; word-line noise immunity; Cellular logic arrays; DRAM chips; Very-large-scale integration;
Conference_Titel :
Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1992.307478
