Scheduling Synchronous Elastic Designs

Author

Carmona, Josep ; Julvez, Jorge ; Cortadella, Jordi ; Kishinevsky, Michael

Author_Institution

Univ. Politec. de Catalunya, Barcelona, Spain

fYear

2009

fDate

1-3 July 2009

Firstpage

52

Lastpage

59

Abstract

Asynchronous and latency-insensitive circuits offer a similar form of elasticity that tolerates variations in the delays of communication resources of a system. This flexibility comes at the expense of including a control layer that synchronizes the flow of information. This paper proposes a method for eliminating the complexity of the control layer, replacing it by a set of iterative schedulers that decide when to activate computations. Unlike previous approaches, this can be achieved with low complexity algorithms and without extra circuitry.

Keywords

asynchronous circuits; electronic engineering computing; scheduling; asynchronous circuits; complexity algorithms; control layer; elasticity; iterative schedulers; latency-insensitive circuits; synchronous elastic designs; Circuits; Clocks; Communication system control; Concurrent computing; Delay; Elasticity; Pipeline processing; Processor scheduling; Registers; Wires; Elastic systems; optimization; scheduling;

fLanguage

English

Publisher

ieee

Conference_Titel

Application of Concurrency to System Design, 2009. ACSD '09. Ninth International Conference on

Conference_Location

Augsburg

ISSN

1550-4808

Print_ISBN

978-0-7695-3697-2

Type

conf

DOI

10.1109/ACSD.2009.12

Filename

5291065