Title :
A buried capacitor DRAM cell with bonded SOI for 256 M and 1 Gbit DRAMs
Author :
Nishihara, T. ; Ikeda, N. ; Aozasa, H. ; Miyazawa, Y. ; Ochiai, A.
Author_Institution :
ULSI Res. & Dev. Group, Sony Corp., Kanagawa, Japan
Abstract :
This paper describes a novel DRAM cell structure using bonded SOI. The cell capacitor is flexibly formed like a stack-capacitor, but buried under the silicon layer. Thus, both a large Cs and small cell size are obtained. Moreover, using a PMOS cell transistor whose back-surface is shielded by a cell plate, the cell leakage current is reduced to 1 fA/cell, resulting in good data retention. Accordingly, a simple scaling of this structure realizes 256 M and 1 Gbit DRAMs.<>
Keywords :
DRAM chips; MOS integrated circuits; VLSI; cellular arrays; semiconductor-insulator boundaries; 1 Gbit; 256 Mbit; DRAMs; PMOS cell transistor; bonded SOI; buried capacitor DRAM cell; cell leakage current; cell plate; cell size; cell structure; data retention; Cellular logic arrays; DRAM chips; MOS integrated circuits; Semiconductor-insulator interfaces; Very-large-scale integration;
Conference_Titel :
Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1992.307480
