Ultra-thin SOI CMOS with selective CVD tungsten for low-resistance source and drain

This paper describes a new ultra-thin SOI-CMOS structure with reduced parasitic diffusion layer resistance. Using a selective CVD tungsten process on the source and drain regions, we experimentally investigate the characteristics of the selectively grown W for SOI layers of various thicknesses (10-200 nm) and CMOS device characteristics. For this structure, the reaction between SOI-Si and W is unnecessary, and the resulting low parasitic diffusion layer resistance and good contact characteristics provide superior device performance.<>