DocumentCode
1954991
Title
ispc: A SPMD compiler for high-performance CPU programming
Author
Pharr, Matt ; Mark, William R.
fYear
2012
fDate
13-14 May 2012
Firstpage
1
Lastpage
13
Abstract
SIMD parallelism has become an increasingly important mechanism for delivering performance in modern CPUs, due its power efficiency and relatively low cost in die area compared to other forms of parallelism. Unfortunately, languages and compilers for CPUs have not kept up with the hardware´s capabilities. Existing CPU parallel programming models focus primarily on multi-core parallelism, neglecting the substantial computational capabilities that are available in CPU SIMD vector units. GPU-oriented languages like OpenCL support SIMD but lack capabilities needed to achieve maximum efficiency on CPUs and suffer from GPU-driven constraints that impair ease of use on CPUs. We have developed a compiler, the Intel R® SPMD Program Compiler (ispc), that delivers very high performance on CPUs thanks to effective use of both multiple processor cores and SIMD vector units. ispc draws from GPU programming languages, which have shown that for many applications the easiest way to program SIMD units is to use a single-program, multiple-data (SPMD) model, with each instance of the program mapped to one SIMD lane. We discuss language features that make ispc easy to adopt and use productively with existing software systems and show that ispc delivers up to 35x speedups on a 4-core system and up to 240× speedups on a 40-core system for complex workloads (compared to serial C++ code).
Keywords
graphics processing units; multiprocessing systems; parallel programming; program compilers; CPU SIMD vector units; GPU programming languages; GPU-oriented languages; ISPC; Intel R SPMD program compiler; OpenCL; SIMD parallelism; high-performance CPU parallel programming; multicore parallelism; multiple processor cores; single-program multiple-data model; Graphics processing unit; Hardware; Parallel processing; Productivity; Programming; Vectors;
fLanguage
English
Publisher
ieee
Conference_Titel
Innovative Parallel Computing (InPar), 2012
Conference_Location
San Jose, CA
Print_ISBN
978-1-4673-2632-2
Electronic_ISBN
978-1-4673-2631-5
Type
conf
DOI
10.1109/InPar.2012.6339601
Filename
6339601
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