Title :
Potential profile engineering for quarter micron buried channel pMOSFETs with n regions in the channel
Author :
Okabe, K. ; Ikezawa, T. ; Sakai, I. ; Fukuma, M.
Author_Institution :
ULSI Device Dev. Labs., NEC Corp., Sagamihara, Japan
Abstract :
A new design approach featured by potential profile engineering is proposed for deep sub-half micron buried channel pMOSFETs by placing n regions within the LDD depletion layers. The newly designed n regions are effective for suppressing drain induced barrier lowering (DIBL) of buried channel pMOSFETs, without any degradation in Vt controllability. Simulation results suggest the potential profile engineering is useful for designing 0.25 mu m buried channel pMOSFETs with high driving capability and good Vt controllability.<>
Keywords :
insulated gate field effect transistors; ion implantation; semiconductor process modelling; 0.25 micron; LDD depletion layers; Vt controllability; drain induced barrier lowering; driving capability; n regions; potential profile engineering; quarter micron buried channel pMOSFETs; Insulated gate FETs; Ion implantation; Semiconductor process modeling;
Conference_Titel :
Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1992.307499
