Three-dimensional characterization of bipolar transistors in a submicron BiCMOS technology using integrated process and device simulation

Author

Pinto, M.R. ; Boulin, D.M. ; Rafferty, C.S. ; Smith, R.K. ; Coughran, W.M., Jr. ; Kizilyalli, Isik C. ; Thoma

Author_Institution

AT&T Bell Labs., Murray Hill, NJ, USA

fYear

1992

fDate

13-16 Dec. 1992

Firstpage

923

Lastpage

926

Abstract

Results of complete 3-dimensional AC/DC characterizations of the n-p-n transistor in a submicron BiCMOS technology are presented. Accuracy and throughput acceptable for constructing compact models is achieved through the use of multidimensional process simulation, adaptive grid generation and preconditioned iterative techniques for both DC and small-signal analysis. Comparisons of 2- and 3-dimensional simulations with measurements enable assessments of the magnitude of 3-dimensional effects, thereby suggesting efficient device optimization strategies.<>

Keywords

BiCMOS integrated circuits; bipolar transistors; digital simulation; electronic engineering computing; semiconductor device models; 3D AC/DC characterizations; adaptive grid generation; bipolar transistors; compact models; device optimization strategies; integrated process/device simulation; multidimensional process simulation; n-p-n transistor; preconditioned iterative technique; small-signal analysis; submicron BiCMOS technology; three-dimensional characterization; BiCMOS integrated circuits; Bipolar transistors; Semiconductor device modeling; Simulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1992.307507

Filename

307507