Title :
A 1.28 mu m/sup 2/ contactless memory cell technology for a 3 V-only 64 Mbit EEPROM
Author :
Kume, H. ; Kato, M. ; Adachi, T. ; Tanaka, T. ; Sasaki, T. ; Okazaki, T. ; Miyamoto, N. ; Saeki, S. ; Ohji, Y. ; Ushiyama, M. ; Yugami, J. ; Morimoto, T. ; Nishida, T.
Author_Institution :
Central Res. Lab., Hitachi Ltd., Kokubunji, Japan
Abstract :
This paper describes a novel contactless memory cell technology for a 3V-only 64Mbit EEPROM with NOR structure. A new program/erase scheme using a Fowler-Nordheim tunneling mechanism is developed, resulting in a single 3V power supply operation. Scatter in "low-level" threshold voltage in a memory array, which seriously affects a read operation margin at a reduced V/sub c/c in the NOR structure, is also improved with this scheme. Based on a 0.4 mu m CMOS process, a small cell area of 1.28 mu m/sup 2/ is successfully realized by the contactless memory cell technology, demonstrating the 64Mbit integration capability.<>
Keywords :
CMOS integrated circuits; EPROM; NOR circuits; integrated circuit technology; integrated memory circuits; 0.4 mum; 3 V; 64 Mbit; CMOS; EEPROM; Fowler-Nordheim tunneling; NOR structure; contactless memory cell technology; low-level threshold voltage; memory array; program/erase scheme; read operation margin; CMOS integrated circuits; EPROM; Integrated circuit fabrication; Semiconductor memories;
Conference_Titel :
Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1992.307524
