An implementation of a hierarchical generalized transversal digital filter

The authors have implemented the two-level hierarchical generalized transversal FIR filter. This chip included nine subfilters and four tapping parts. Each subfilter had exactly the same filter characteristics and the coefficients of each tapping part were the same. This highly parallel structure allowed the reduction of the number of control bits, the number of filter sequences, the chip size, and the operation time. It only needed up to 32 words and 16 bits of machine-level control sequence. Up to 21-MHz clock speed and 3 MHz sampling speed was available. The 5.4×5.5 mm chip was fabricated using 1.2-μm double-level metal CMOS technology with 44 pins flat or PLCC package