• DocumentCode
    19564
  • Title

    A Dual-Material Gate Junctionless Transistor With High- k Spacer for Enhanced Analog Performance

  • Author

    Baruah, Ratul Kumar ; Paily, Roy P.

  • Author_Institution
    Dept. of Electron. & Electr. Eng., Indian Inst. of Technol. Guwahati, Guwahati, India
  • Volume
    61
  • Issue
    1
  • fYear
    2014
  • fDate
    Jan. 2014
  • Firstpage
    123
  • Lastpage
    128
  • Abstract
    In this paper, we present a simulation study of analog circuit performance parameters for a symmetric double-gate junctionless transistor (DGJLT) using dual-material gate along with high- k spacer dielectric (DMG-SP) on both sides of the gate oxides of the device. The characteristics are demonstrated and compared with DMG DGJLT and single-material (conventional) gate (SMG) DGJLT. The DMG DGJLT presents superior transconductance (Gm), early voltage (VEA), and intrinsic gain (GmRO) compared with SMG DGJLT. The values are further improved for DMG-SP DGJLT, because high- k spacer enhances the fringing electric fields through the spacer.
  • Keywords
    MOSFET; high-k dielectric thin films; analog circuit performance; dual material gate junctionless transistor; enhanced analog performance; fringing electric field enhancement; high-k spacer dielectric; symmetric double gate junctionless transistor; Dielectrics; Electric potential; High K dielectric materials; Logic gates; Performance evaluation; Semiconductor process modeling; Transconductance; Dual-material gate (DMG); high-$k$ spacer; intrinsic gain; junctionless transistor (JLT); unity gains cutoff frequency; workfunction;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2013.2292852
  • Filename
    6680718
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=19564