Title :
CMOS-SRAM soft-error simulation system
Author :
Satoh, Shigeo ; Sude, R. ; Tashiro, Hiroko ; Higaki, Naoshi ; Nakayama, Noriaki
Author_Institution :
Fujitsu Labs. Ltd., Atsugi, Japan
Abstract :
A soft-error simulation system for designing CMOS-SRAM cells is presented. We propose a new noise current model and combine it with the SRAM´s equivalent circuit. Simulation results agree with those from a compulsory exposure experiment. Our system predicts the field soft-error rate from the alpha-particle emission rate, mask layout, and process conditions.<>
Keywords :
CMOS integrated circuits; SRAM chips; alpha-particle effects; circuit analysis computing; digital simulation; equivalent circuits; errors; semiconductor device models; semiconductor device noise; CMOS-SRAM; alpha-particle emission rate; equivalent circuit; field soft-error rate; mask layout; noise current model; process conditions; soft-error simulation system; static RAM cell design; Alpha particles; Charge carrier processes; Circuit noise; Circuit simulation; Equivalent circuits; Laboratories; Predictive models; Random access memory; Surfaces; Voltage;
Conference_Titel :
Reliability Physics Symposium, 1994. 32nd Annual Proceedings., IEEE International
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-1357-7
DOI :
10.1109/RELPHY.1994.307815
