• DocumentCode
    1956509
  • Title

    Comparison of ESD protection capability of SOI and bulk CMOS output buffers

  • Author

    Chan, Mansun ; Yuen, Selina S. ; Ma, Zhi-Jian ; Hui, Kelvin Y. ; Ko, Ping K. ; Hu, Chenming

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
  • fYear
    1994
  • fDate
    11-14 April 1994
  • Firstpage
    292
  • Lastpage
    298
  • Abstract
    ESD protection capability of SOI CMOS output buffers has been studied with human body model (HBM) stresses of both positive and negative polarity. Experimental results show that the ESD discharge current is absorbed by the NMOSFET alone. Unlike bulk technologies where the bi-directional ESD failure voltages are limited by positive polarity stresses, SOI circuits display a more serious reliability problem in handling negative ESD discharge current. Bulk NMOS output buffers fabricated on the substrate of the same SOI wafers, after etching away the buried oxide, have been used to compare the ESD protection capability between bulk and SOI technologies. The ESD voltage sustained by these "bulk" NMOS buffers is about twice the voltage sustained by conventional SOI NMOS buffers. This scheme is proposed as an alternative ESD protection for SOI circuits. The effectiveness of ESD resistant design strategies developed in bulk-substrate technologies when transferred to SOI circuits is also discussed in this paper.<>
  • Keywords
    CMOS integrated circuits; buffer circuits; circuit reliability; electrostatic discharge; insulated gate field effect transistors; protection; reliability; semiconductor-insulator boundaries; ESD discharge current; ESD protection capability; ESD resistant design strategies; NMOSFETs; SOI CMOS output buffers; SOI circuits; bi-directional ESD failure voltages; bulk CMOS output buffers; bulk-substrate technologies; buried oxide; etching; human body model stresses; negative ESD discharge current; negative polarity; positive polarity; positive polarity stresses; reliability problem; Biological system modeling; CMOS technology; Electrostatic discharge; Humans; MOS devices; MOSFET circuits; Protection; Semiconductor device modeling; Stress; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium, 1994. 32nd Annual Proceedings., IEEE International
  • Conference_Location
    San Jose, CA, USA
  • Print_ISBN
    0-7803-1357-7
  • Type

    conf

  • DOI
    10.1109/RELPHY.1994.307821
  • Filename
    307821