Multiple layers of silicon-on-insulator (MLSOI) islands fabrication process and fully-depleted SOI pMOSFETs

Summary form only given. As device scaling approaches ever smaller regimes, multiple layer device fabrication is necessary to increase chip integration up to and beyond the gigascale regime. This paper presents multiple layer SOI (MLSOI) islands fabricated using Si SEG and ELO. The MLSOI fabrication process used was an extension of the single layer SOI island process (Neudeck et al, 1997). The first SOI layer was created by forming oxide wells via oxidation, RIE oxide etch, and re-oxidation. Adjacent to the wells, a SEG/ELO seed window is opened. SEG/ELO was grown from the seed window and laterally over the field oxide until the recessed oxide wells were filled. Excess SEG/ELO over the recess wells was removed by CMP down to the field oxide level, isolating Si in the recessed wells from the seed and thus creating SOI active device islands. The second SOI layer was similarly fabricated, but a PECVD oxide was used to create the next recessed well layer. The PECVD oxide layer wells were created by timed RIE or wet etching, but an intermediate etch stop layer can be incorporated by using LPCVD Si/sub 3/N/sub 4/ prior to oxide PECVD. By repeating the fabrication process presented, additional SOI layers can be fabricated. The potential benefits of MLSOI designs are immense. Packing densities can be dramatically increased. Different device processes can be incorporated into the different MLSOI layers, e.g. making pMOSFETs on one layer and nMOSFETs on another. By designing two SRAM cells (using eight nMOSFETs and four pMOSFETs) in three Si layers with pMOSFETs in the middle layer between nMOSFET layers, area saved is about 3/spl times/.