DocumentCode
1956539
Title
Designing latchup robustness in a 0.35 /spl mu/m technology
Author
Amerasekera, Ajith ; Selvam, S. Tamizh ; Chapman, Richard A.
Author_Institution
Semicond. Process & Device Center, Texas Instrum. Inc., Dallas, TX, USA
fYear
1994
fDate
11-14 April 1994
Firstpage
280
Lastpage
285
Abstract
We have explored the technology design space for latchup robustness in a deep submicron process. We show using experimental data that latchup robustness can be designed into a deep submicron technology without the use of retrograde wells or trench isolation. The main parameters affecting the latchup holding voltage and the trigger current have been investigated. The application of simulations and empirical models for tailoring latchup holding voltages are also discussed.<>
Keywords
CMOS integrated circuits; digital simulation; integrated circuit technology; semiconductor device models; 0.35 /spl mu/m technology; 0.35 micron; CMOS IC; deep submicron process; latchup holding voltage; latchup robustness; trigger current; Anodes; Boron; Cathodes; Current measurement; Epitaxial layers; Pulse measurements; Robustness; Substrates; Testing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium, 1994. 32nd Annual Proceedings., IEEE International
Conference_Location
San Jose, CA, USA
Print_ISBN
0-7803-1357-7
Type
conf
DOI
10.1109/RELPHY.1994.307823
Filename
307823
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