Title :
A 32-bit microprocessor with high performance bit-map manipulation instructions
Author :
Shimizu, Toru ; Iwata, Shunichi ; Saito, Yuichi ; Yoshida, Toyohiko ; Matsuo, Masahito ; Hinata, Junichi ; Saito, Kazunori
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
Abstract :
The GMICRO/100, a 32-b microprocessor based on the TRON architecture specification, is described. The GMICRO/100 uses high-level instructions, such as those in bit-map manipulation. The bit-map instructions are implemented by pipelining micro-operations, and achieve optimum use of the memory bus in the execution. The bit-map instructions are 2 to 3 times faster than repeating move instructions by the software. Microprogram development tools for the GMICRO/100 design are described
Keywords :
computer graphic equipment; microprocessor chips; 32 bit; 32-bit microprocessor; GMICRO/100; TRON architecture specification; bit-map manipulation instructions; high-level instructions; memory bus; micro-operations; microprogram development tools; pipelining; Arithmetic; CMOS process; Clocks; Computer architecture; Embedded system; Laboratories; Large scale integration; Microprocessors; Pipeline processing; Research and development;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63397
