Title :
Effect of body-to-source bias on the analog characteristics of 0.35 /spl mu/m partially depleted SOI CMOS for low-voltage low-power mixed-mode applications
Author :
Babcock, J.A. ; Francis, P. ; Haggag, H. ; Darmawan, J. ; Lee, T.-W. ; Lindorfer, P. ; Olgaard, C. ; Merrill, R.B. ; Schroder, D.K.
Author_Institution :
Nat. Semicond. Corp., Santa Clara, CA, USA
Abstract :
A 3.3 V 0.35 /spl mu/m CMOS process, implemented on 8-inch bonded SOI wafers, is investigated for low-voltage low-power analog applications. Enhanced low-power analog performance is demonstrated by applying a forward biased body-source voltage which enables reduced short channel effects and a flatter threshold voltage response as a function of drawn gate length. Furthermore, this paper demonstrates that the onset of fully-depleted (FD) operation as a function of reverse body-to-source bias is highly sensitive to the channel length.
Keywords :
CMOS integrated circuits; integrated circuit testing; mixed analogue-digital integrated circuits; silicon-on-insulator; wafer bonding; 0.35 micron; 3.3 V; CMOS process; Si-SiO/sub 2/; analog characteristics; body-to-source bias effect; bonded SOI wafers; channel length; drawn gate length; enhanced low-power analog performance; forward biased body-source voltage; fully-depleted operation; low-power mixed-mode applications; low-voltage low-power analog applications; low-voltage mixed-mode applications; partially depleted SOI CMOS; reverse body-to-source bias; short channel effects; threshold voltage response; Analog circuits; Bonding; CMOS process; CMOS technology; Electrical resistance measurement; Length measurement; MOSFETs; Silicon on insulator technology; Solid state circuits; Threshold voltage;
Conference_Titel :
SOI Conference, 1998. Proceedings., 1998 IEEE International
Conference_Location :
Stuart, FL, USA
Print_ISBN :
0-7803-4500-2
DOI :
10.1109/SOI.1998.723093
