Design and test of a bit parallel 2nd order IIR filter structure

Author

Nally, O. C Mc ; Marnane, W.P. ; Canny, J. V Mc

Author_Institution

Dept. of Electr. & Electron. Eng., Queen´´s Univ. of Belfast, UK

fYear

1991

fDate

14-17 Apr 1991

Firstpage

1189

Abstract

Test procedures for a pipelined bit-parallel IIR filter chip which maximally exploit its regularity are described. It is shown that small modifications to the basic architecture result in significant reductions in the number of test patterns required to test such CMOS chips. The methods used allow 100% fault coverage to be achieved using less than 1000 test vectors for a chip which has 12 bit data and coefficients

Keywords

CMOS integrated circuits; digital filters; electronic equipment testing; parallel architectures; 12 bit; 2nd order IIR filter; CMOS; digital filter; fault coverage; pipelined bit-parallel filter; test patterns; test procedures; test vectors; Arithmetic; Circuits; Clocks; Delay; Equations; IIR filters; Microelectronics; Pipeline processing; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Acoustics, Speech, and Signal Processing, 1991. ICASSP-91., 1991 International Conference on

Conference_Location

Toronto, Ont.

ISSN

1520-6149

Print_ISBN

0-7803-0003-3

Type

conf

DOI

10.1109/ICASSP.1991.150593

Filename

150593

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1957572