DocumentCode :
1957629
Title :
3-D simulation analysis of high performance SOI lateral BJT for RF applications
Author :
Kawanaka, S. ; Fuse, T. ; Inoh, K. ; Shino, T. ; Nii, H. ; Yamada, T. ; Yoshimi, M. ; Watanabe, S.
Author_Institution :
Adv. Semicond. Device Res. Lab., Toshiba Corp., Kawasaki, Japan
fYear :
1998
fDate :
5-8 Oct. 1998
Firstpage :
29
Lastpage :
30
Abstract :
Summary form only given. In view of the rapid growth of the portable wireless communications market, the development of low-power and low-cost RF device technology is becoming important. The SOI lateral BJT has attracted considerable interest due to its low parasitic capacitance and simplified process. However, in the previous reports (Higaki et al. 1991; Shahidi et al. 1991; Babcock et al, 1996), the maximum f/sub max/ is less than half that of conventional bulk Si counterparts. This is presumably due to the high base-resistance (R/sub b/). In this work, we propose novel and practical SOI lateral BJTs which feature drastically reduced R/sup b/. A maximum operating frequency (f/sub max/) as high as 111 GHz is predicted.
Keywords :
capacitance; electric resistance; microwave bipolar transistors; millimetre wave bipolar transistors; semiconductor device models; silicon-on-insulator; 111 GHz; 3D simulation analysis; RF applications; SOI lateral BJT; Si-SiO/sub 2/; base-resistance; low-cost RF device technology; low-power RF device technology; maximum operating frequency; parasitic capacitance; portable wireless communications market; Analytical models; Delay effects; Electrons; Performance analysis; Radio frequency;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI Conference, 1998. Proceedings., 1998 IEEE International
Conference_Location :
Stuart, FL, USA
ISSN :
1078-621X
Print_ISBN :
0-7803-4500-2
Type :
conf
DOI :
10.1109/SOI.1998.723095
Filename :
723095
Link To Document :
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