DocumentCode :
1957652
Title :
Automatic synthesis and technology mapping of combinational logic
Author :
Bergamaschi, R.A.
Author_Institution :
Dept. of Electron. & Comput. Sci., Southampton Univ., UK
fYear :
1988
fDate :
7-10 Nov. 1988
Firstpage :
466
Lastpage :
469
Abstract :
SKOL, a system for the synthesis of combinational logic using a library of cells that emphasizes technology-mapping algorithms, is described. It combines current multilevel optimization techniques with a novel approach to technology mapping. Each factor (or the factorized Boolean equation) can be implemented by itself or collapsed into the higher level expression containing it, which is then implemented. An expression can be implemented in several ways, which differ in the degree of factorization. A number of selected implementations is evaluated and the one with minimal cost (area or delay) is chosen. The mapping algorithms are independent of the library of cells, which can be easily modified. Results from benchmark examples were better than or comparable to those for existing systems.<>
Keywords :
Boolean functions; circuit layout CAD; logic CAD; minimisation of switching nets; SKOL; combinational logic; factorized Boolean equation; multilevel optimization; technology-mapping algorithms; Automatic logic units; Computer science; Costs; Delay; Design optimization; Equations; Isolation technology; Kernel; Libraries; Logic design;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-0869-2
Type :
conf
DOI :
10.1109/ICCAD.1988.122550
Filename :
122550
Link To Document :
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